Synchronous V/S Asynchronous FIFO Design
Dr. Shailaja Mudengudi, Komal L Mane, Laxmi B Amargol, Vani S Sarvi
This project presents the design, implementation, and comparative analysis of Synchronous FIFO and Asynchronous FIFO architectures using Verilog HDL and EDA tools. FIFO (First-In-First-Out) memories are widely used in digital systems for temporary data storage and reliable communication between subsystems. However, designing FIFO architectures that ensure high speed, low power, and reliable clock-domain crossing remains challenging.