Article’s

Efficient communication between high-speed and low-speed components in System-on-Chip (SoC) architectures requires reliable protocol conversion mechanisms. The AMBA AHB (Advanced High-Performance Bus) and APB (Advanced Peripheral Bus) represent two widely adopted communication protocols serving distinct classes of system components. This work presents the complete design, RTL implementation, simulation, and synthesis analysis of an AHB to APB protocol converter. The bridge translates high-speed, pipelined AHB transactions into simple, non-pipelined APB operations using a finite-state-machine (FSM)-based controller. The architecture supports a single AHB master, four APB slaves, and parameterized 512-bit wide data/address paths. Functional verification is performed using Cadence Xcelium, while synthesis and timing analysis are carried out using Cadence Genus. Simulation confirms correct protocol conversion, APB sequencing, and data handling. Synthesis results further validate area feasibility, clock performance around 100 MHz, and predictable power consumption. This work demonstrates a complete, synthesizable AMBA-compliant bridge suitable for SoC subsystem integration