Author(s) :

Dr. Shailaja Mudengudi, Komal L Mane, Laxmi B Amargol, Vani S Sarvi .

Volume/Issue :

Abstract :

This project presents the design, implementation, and comparative analysis of Synchronous FIFO and Asynchronous FIFO architectures using Verilog HDL and EDA tools. FIFO (First-In-First-Out) memories are widely used in digital systems for temporary data storage and reliable communication between subsystems. However, designing FIFO architectures that ensure high speed, low power, and reliable clock-domain crossing remains challenging.

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