Design and Implementation of High-speed Low-power FIR filter using Cadence tool
Dr. Shailaja Mudengudi, Ankita Londve, Deepa Hanamasagar, Prajwal P Danappagoudar
Finite Impulse Response (FIR) filters are widely used in modern digital signal processing systems that demand high computational speed, low power consumption, and efficient silicon area utilization. This project presents the design and implementation of a high-speed, low-power FIR filter using the Cadence design environment. The proposed architecture employs an optimized multiplier-accumulator (MAC) structure, coefficient symmetry exploitation, and pipelined data paths to minimize critical path delay and reduce overall dynamic power consumption. RTL design was developed using Verilog HDL and synthesized using Cadence Genus, while Cadence power–performance–area (PPA) analysis. Post-layout simulations validate the correctness of the filter and demonstrate significant improvements in maximum operating frequency and power efficiency compared to conventional FIR filter implementations. The results confirm that the proposed design methodology is suitable for high-performance DSP applications such as wireless communication, biomedical signal processing, and real-time embedded systems.