Designing and implementation of 32-bit RISC Processor using verilog HDL
Lavanya N Kurahatti, Kavya B Ramasali, Keerti V Navalagunda
This paper presents the design and implementation of a 32-bit RISC processor using Verilog HDL. The processor follows a simplified instruction set and pipelined architecture to achieve higher performance and reduced hardware complexity. The design includes basic processing units such as ALU, register file, control unit, and memory modules. The processor is verified using simulation tools and synthesized for FPGA implementation. The proposed design is suitable for educational and embedded system applications.